When outputting data during a write operation to a data storage system such as a disk drive, it is sometimes advantageous to delay a clock edge slightly in order to precompensate for data interaction on the storage medium. For disk storage media and other storage media, this delay is variable in length in order to optimize efficient data storage on the disk or other storage medium.
Prior systems and methods of allowing for this delay have interposed a delay element in the clock signal path which can be selectively triggered depending upon the data being written. However, in high data transfer rate operations, the time necessary for the delay element to settle on an appropriate delay time reduces the throughput available to the integrated system.